PCIe 6.0 and CXL: The Future of Internal Interconnects

## PCIe 6.0 Specs

| Feature | PCIe 5.0 | PCIe 6.0 |
|---|---|---|
| Per-lane | 32 GT/s | 64 GT/s |
| x16 bandwidth | 64 GB/s | 128 GB/s |
| Encoding | 128b/130b | PAM-4 + 242B/256B |
| FLIT mode | Optional | Mandatory |

## PAM-4 Signaling

PCIe 6.0 uses PAM-4 (4-level pulse amplitude modulation) instead of NRZ (2-level). This doubles throughput per pin but requires error correction (CRC + FEC), adding ~5% overhead.

## CXL: Beyond PCIe

Compute Express Link runs over PCIe physical layer but adds:
- **CXL.mem**: Shared memory pools between CPU and devices
- **CXL.cache**: Cache-coherent access to device memory
- **CXL.io**: Standard PCIe I/O

## Impact on Consumer Cables

PCIe 6.0 flows through Thunderbolt and USB4. Future Thunderbolt versions over USB-C will deliver 160+ Gbps, enabling:
- External NVMe RAID arrays at internal speeds
- 8K multi-display from a single cable
- External AI accelerators